1. Field of the Invention
The present invention relates to packet transmitting/receiving apparatus and method for a computer system for transmitting a command between modules such as host, memory, input/output devices, and the like. More particularly, the invention relates to packet transmitting/receiving method and apparatus for a computer system, in which even in a packet transfer waiting state, with respect to a packet having a high priority, the transfer waiting state is withdrawn, thereby enabling such a packet to be preferentially transferred.
2. Description of the Related Arts
Hitherto, in a computer system in which a host, a memory unit functioning as a main storage, and input/output devices are distributed and arranged, the host, memory unit, and input/output devices are connected by a PCI bus (Peripheral Component Interconnect bus) known as a high speed extension bus. On the other hand, in association with the improvement of processing performance and the realization of a high processing speed of a CPU in recent years, a system in which the host, memory unit, and input/output devices connected to the PCI bus are connected by a packet network (packet bus) has been proposed.
FIG. 1 is a schematic diagram of a computer system using packet transmission/reception. Hosts 110-1 and 110-3 are connected to PCI buses 108-1 and 108-3 by PCI modules 112-1 and 112-3, respectively. The PCI buses 108-1 and 108-3 are connected to a packet transmitting/receiving module 100 by PCI bridge modules 106-1 and 106-3, respectively. Memory modules 114-2 and 114-4 each functioning as a main storage are connected to other PCI buses 108-2 and 108-4. The PCI buses 108-2 and 108-4 are also connected to the packet transmitting/receiving module 100 via PCI bridge modules 106-2 and 106-4. The transmitting/receiving module 100 has packet transmitting/receiving units 102-1, 102-2, 102-3, and 102-4 and they are connected by a packet bus 104. The operation of the computer system is performed, for example, as follows. When the host 110-1 generates, for example, a write command, the PCI module 112-1 transfers the write command (including a command code, an address, and data) to the bridge module 106-1. When the transfer through the bus is completed, the PCI bridge module 106-1 converts the write command into a packet and transfers such a write packet from the packet transmitting/receiving unit 102-1 of the packet transmitting/receiving module 100 to, for example, the packet transmitting/receiving unit 102-4 on the memory module 114-4 side. The packet received by the packet transmitting/receiving unit 102-4 is converted into a PCI write command by the PCI bridge module 106-4 and transferred to the memory module 114-4 through the PCI bridge module 112-4 by the PCI bus 108-4, thereby writing data. The packet transfer in the packet transmitting/receiving module 100 is performed as follows. The packet transmitting/receiving unit 102-1 as a transmitting source first generates a transmitting request to the packet transmitting/receiving unit 102-4 as a transmission destination. When transmission permission is obtained, the unit 102-1 transmits the packet. When the transmission permission is not obtained, the unit 102-1 enters a transfer waiting state with the transmission packet stored in a buffer. When the buffer is full in the transfer waiting state, the packet reception from the PCI bridge module 106-1 is inhibited. When the packet transmitting/receiving unit 102-4 on the transmission destination side receives the transmitting request from the packet transmitting/receiving unit 102-1, there is an empty space in the buffer. If there is no error in the external PCI bridge module 106-4, the unit 102-4 is in a packet receivable state. Accordingly, the unit makes a response of the transmission permission and receives the packet. On the contrary, when the buffer of the packet transmitting/receiving unit 102-4 is full or the unit 102-4 is in a packet unreceivable state due to an error caused by a failure or the like of the PCI bridge module 106-4, a response of the transmission permission is inhibited. In correspondence to the stop of the response regarding the transmission permission, the packet transmitting/receiving unit 102-4 on the transmission destination side enters the transfer waiting state.
However, in such a packet transmission/reception, in the case where the transmitting request is issued to a specific packet transmitting/receiving unit and an acknowledgment response is not obtained and the unit enters the transfer waiting state, even if another packet transmitting/receiving unit is in the receivable state, all of the packet transfer operations are obstructed in the transfer waiting state, so that the packet transmitting/receiving function is impeded. Particularly, when the packet which entered the transfer waiting state is a response packet (replay packet) after a command system packet is transferred, a packet sequence enters a transfer waiting state on the halfway, so that it results in a serious factor of deteriorating processing performance of the packet transfer. When the PCI bridge module 106-4 externally connected to the packet transmitting/receiving unit 102-4 on the transmission destination side can not obtain the acknowledgment response due to an error such as a failure of hardware or the like, the transfer waiting state of the packet transmitting/receiving unit 102-1 on the transmitting source side is not cancelled, so that such a problem that the unit is hung up also occurs.